The invention relates to signal processing and device testing involving high-speed digital signals. In particular, the invention relates to reducing input transition rates when performing signal processing with digital devices and during testing of high-speed digital devices.
Clock rates in digital systems and the semiconductor devices or integrated circuits (ICs) that invariably make up the systems continue to increase. Associated with the increases in clock rates is an increase in data rates of signals generated by the digital systems. The data rate of a digital signal is proportional to the rate of logic transitions found in the signal and is sometimes referred to as the transition rate. Increases in transition rates of signals produced by modem digital systems are expected to continue for the foreseeable future.
Rapid or high transition rates typical of the signals generated by modem digital systems pose a problem for components and systems that must receive and process these signals. As transition rates increase, the cost and complexity of these so-called xe2x80x98downstreamxe2x80x99 components and systems tend to increase dramatically. In an analogous manner, fast transition rates of the signals generated by modem digital systems also significantly increase the difficulty of adequately and accurately testing these systems. At the very least, the fast transition rate of the high speed signals tend to significantly increase the cost of the test equipment required for adequate testing. In addition, relatively expensive test equipment is often rendered obsolete by increases in transition rates over time. Obsolescence of modem test equipment associated with transition rate increases can occur in a very short time given the current frenetic pace of clock and transition rate increases.
To avoid the use of high speed, expensive downstream components and to avoid the need for upgrading or replacing test equipment to accommodate increases in transition rates, it is sometimes attractive to employ approaches to signal processing and/or testing that attempt to reduce the maximum transition rates of the signals of interest. In essence, the maximum transition rate experienced by downstream components and/or test equipment can be reduced in some cases by inserting a transition rate-reducing device between the component or piece of test equipment and the digital system generating the signal. If the transition rate can be reduced while simultaneously maintaining the integrity of the data contained in the signal, lower cost components can be used to process the signal and/or test the device that generated the signal. The discussion that follows, while focusing on test equipment for simplicity, applies equally well to any downstream component that must receive and process high-speed signals.
One approach to reducing transition rates is known as frequency division. This approach is most effective for signals, such as clock signals that are relatively narrowband. A device known as a frequency divider reduces the frequency or transition rate of a signal. Typically, frequency dividers for digital signals are implemented using one or more flip-flops and provide integer division of the input frequency. However, this approach is not particularly useful for signals that contain data since these signals are typically not narrowband. Moreover, frequency division of signals that contain data typically results in the loss of some of the data of the signal. Loss of data is normally unacceptable. Thus, this technique is most often used for reducing the transition rate of signals, such as clock signals, that contain little or no data. The concept of frequency division of a clock signal is illustrated in FIG. 1A. In FIG. 1A, a frequency divider 10 with a division factor of two is illustrated operating on a clock signal.
Another approach to transition rate reduction, sometimes referred to as xe2x80x98samplingxe2x80x99, employs a waveform sampler between the device under test (DUT) and the test equipment. The signal is sampled by the waveform sampler to produce two or more sub-signals, each containing a portion of the data contained in the original, higher speed signal. The two or more sub-signals each have a lower transition rate than the original signal. Several parallel channels within the test equipment then process the sub-signals. For example, in one implementation, odd numbered samples of the waveform are contained in a first sub-signal and are processed by a first channel, while even numbered samples are contained in a second sub-signal and are processed by a second channel. Typically the channels of the test equipment operate in parallel to simultaneously process the sub-signals.
The sampling concept is illustrated in FIG. 1B and FIG. 1C. As illustrated in FIG. 1B, a signal under test Sin is sampled by a sampler. The sampler is clocked by a clock signal CLK and samples are taken at both the rising and falling edges of the clock signal. The sampler produces two sub-signals A and B as illustrated in FIG. 1B. Sub-signal A represents the amplitudes of samples of the signal under test Sin at odd numbered sample intervals corresponding in this case to rising edges of the sampling clock signal CLK. Sub-signal B represents samples at even numbered sample intervals taken at falling edges of the clock signal CLK. Two parallel channels are used in the test equipment (not illustrated) to simultaneously process the sub-signals A and B. Once processed, bit level information of the original signal under test can be extracted. The effective transition rate reduction for the example illustrated is a factor of two. Further reductions in the maximum transition rate can be ,realized with the addition of more parallel channels, more delayed versions of the clock signal CLK, and more sub-signals.
FIG. 1C illustrates one implementation of a sampler 20. As illustrated, the sampler comprises a first D flip-flop 22 and a second D flip-flop 24. The signal under test Sin is applied to data inputs of the first and second D flip-flops 22, 24. The sampling clock signal CLK is applied to a clock input of the first D flip-flop. An inverse of the clock signal CLK is applied to a clock input of the second D flip-flop 24. Each rising edge of the clock signal CLK causes the first D flip-flop 22 to sample the signal Sin while each falling edge of the clock signal causes the second D flip-flop 24 to sample the signal Sin. The sub-signals A and B are output at outputs Q of the first and second D flip-flops 22, 24 respectively.
The samples in the sampling approach described hereinabove are generally treated and can be viewed as two or more interleaved signals from a processing standpoint. Typically in this approach, the sampler measures signal amplitude at each sample point. Therefore, information regarding digital signal transition timing is generally unavailable except at a coarse level. In addition, careful synchronization of the sampler and the signal under test is often required to insure the validity and usefulness of the samples in the sub-signals.
Accordingly, it would be advantageous to have an apparatus and method for use in testing and/or processing of digital signals that significantly improved the frequency scalability of test equipment or downstream communications signal processing components, for example, by reducing the maximum transition rate of the signals. In addition, it would be desirable that such an apparatus and method, while reducing the maximum transition rate of the signal, preserved transition timing information of the signal, thereby enabling precision timing tests to be performed on the DUT or enabling downstream precision signal processing. Moreover, it would be desirable that such an apparatus and method could be realized without requiring tight synchronization to the signal under test or the use of a synchronized clock signal and that such an apparatus and method could be implemented using standard, readily available components. Such an apparatus and method would solve long-standing needs in the area of communications and high transition rate digital IC and system testing.
The present invention provides a novel transition splitter apparatus and method for reducing a maximum transition rate of digital signals. The novel apparatus of the present invention is particularly useful in digital signal processing and for performing digital transition timing testing on a device under test. The apparatus splits a digital signal into two or more signals while preserving the timing of transitions in the signal. The transition splitting apparatus of the present invention is implemented with readily available components and reduces the maximum transition rate of a digital signal by at least a factor of two. With the transition splitting apparatus of the present invention, a high frequency signal is partitioned into two equivalent lower frequency signals without loss of any information, including transition timing information. The transition splitting apparatus can be cascaded to achieve greater reductions in maximum transition rates.
In one aspect of the present invention, a transition splitter apparatus for reducing a transition rate of a digital signal while preserving relative transition timing of the digital signal is provided. The apparatus of the present invention comprises an input port that receives the digital signal, a plurality of K output ports, where K is an even number greater than or equal to 2, and a splitter connected between the input port and the K output ports. The splitter produces a different output signal at each output port having transitions corresponding to occurrences of a particular transition type in the digital signal. Thus, each output signal has a fraction of the data or transition rate of the digital signal, and as such, each output signal has a fraction of the number of transitions and a fraction of the transition timing in the digital signal. Assuming that no transition types existing in the digital signal are ignored, the fractional transition rate is proportional to the number K of the output signals provided by the splitter.
In one embodiment of the transition splitter apparatus, K is equal to 2 and the splitter comprises two data or D latches and an inverter connected to the enable input one of the latches. Each data latch produces a different output signal that has a reduced transition rate relative to the transition rate of the digital signal. The digital input signal is received at a first latch enable input of a first of the latches and the inverter connected to the enable input of a second of the latches. The input signal comprises different transition types, such as a transition from a low logic state to a high logic state and a transition from a high logic state to a low logic state. Another transition type may be the timing or occurrence of a particular transition. The output signals from the data latches each have a different set of transitions corresponding to occurrences and/or types of transitions in the input signal. One transition type will enable the first data latch and disable the second data latch, such that the enabled first latch will produce a transition in its respective output signal. Another second transition type will enable the second data latch and disable the first data latch, such that a transition is produced in the output signal of the enabled second latch. The sum of the reduced transition rates (or number of transitions per unit time) of the first output signal and of the second output signal equals the transition rate of the original digital input signal being processed, or tested from the a device under test, depending on the application.
In other embodiments of the transition splitter apparatus, K is equal to 2 and the splitter comprises either two data flip-flops or two toggle flip-flops. Similar to the data latch embodiment, one transition type in the digital input signal will clock a first of the flip-flops, but not the other, such that the output signal from the clocked flip-flop will have a transition corresponding to the occurrence of this transition type. Another transition type in the input signal will clock a second of the flip-flops, but not the first, such that the output signal from the clocked second flip-flop will have a transition corresponding to the occurrence of this other transition type.
In another aspect of the present invention, a transition splitter apparatus that produces K output signals is provided, where K is preferably greater than 2. According to this embodiment, the transition splitter comprises an input port that receives a digital signal, K output ports, and K splitters connected together as a cascade. Each of the K output signals comprises a fraction of the number of transitions that is proportional to K, while preserving relative timing of the transitions in the digital signal. In one embodiment, the splitters are transparent data latches each having a data input, an enable input and an output. The input port is connected to each of the latch enable inputs, such that the enable input of every other latch is invertedly connected to the input port. The output of each latch is connected to a different one of the K output ports. In addition, each output of a first latch to a Kxe2x88x921 latch is further connected to the data input of a respective subsequently adjacent latch in the cascade while the output of the K-th latch is further invertedly connected to the data input of the first latch.
In yet another aspect of the present invention, a first method and a second method of transition splitting a digital signal are provided. Each method splits the digital input signal into a plurality of output signals that can be further processed, either by test equipment or communications digital signal processing equipment, for example. The input signal has a number of transitions per second. Each output signal has a fraction of the number of transitions per second of the input signal. The first method comprises the steps of detecting a transition in the input signal and determining the type of the detected transition. One of a plurality of output signals is chosen to correspond with the transition type and an output transition is created in the chosen output signal. The steps of detecting, determining, choosing and creating are repeated for each transition in the input signal, such that the relative timing of each of the transitions in the input signal is preserved.
The second method according to the invention comprises the steps of selecting an output signal from the plurality of output signals, detecting a transition in the input signal and creating an output transition in the selected output signal corresponding to the detected input signal transition. The above steps are repeated for a number of transitions in the digital input signal, such that relative timing of the transitions in the digital signal is preserved. The number of transitions detected can be all transitions or less than all transitions in the digital input signal. When less than all transitions in the input signal are detected, the method steps may be repeated to detect those transitions that were not originally detected.
In still another embodiment of the present invention, a system or cascade of transition splitter apparatuses is provided. The system splits a digital input signal into a plurality of output signals, each output signal having a fraction of a transition rate of the input signal. The system comprises a first tier transition splitter having a first input that receives the input signal and two first outputs. The first tier transition splitter produces different first output signals. The first tier output signals each having one half of the transition rate of the input signal. The system further comprises a pair of second tier transition splitters. Each second transition splitter has a second input and two second outputs. Each one of the first tier output signals is received by a different one of the second tier inputs. Both of second tier transition splitters produce two different second tier output signals. The second tier output signals each have one fourth of the transition rate of the original input signal. The system of transition splitters has 2M outputs, where M is the number of tiers. Each output signal from a system output has fraction of the transition rate of the original digital input signal that is proportional to 2M and preserves the relative timing of the transitions in the original input signal.
In still another aspect of the invention, a method of reducing the transition rate of a digital signal is provided. The method comprises the steps of cascading a plurality of transition splitters together in a number of tiers and reducing the transition rate by a reduction factor equal to 2M in the output signals, where M is the number of tiers, while preserving relative transition timing of the digital signal. Each tier comprises an increasing number of splitters per tier and the output signals from a splitter in one tier becomes the input signals to two different splitters in an adjacent greater tier.